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Basic of Digital Electronics

November 10, 2012

Image For hardware interview you will have to know your DSD class very well. Review your logic gates, definition of buffer, multiplexer, FIFO, and etc. Let’s start review: Review: Part 1: On a periodic signal:

Duty cycle: Pulse width/Period

Rise time:  time from %10 of pulse amplitude to %90 of pulse amplitude [For the step function]

Fall time: time from %90 of pulse amplitude to %10 of pulse amplitude [For the step function]

Transition time: Switching time between two valid states: can be Rise time or Fall time [For the step function]

Propagation delay/gate delay: Time that response changes from initial value to %50 of final value. Propagation delay increases with operating temperature.The term low,high speed comes from propagation delay. Wires have an approximate propagation delay of 1 ns for every 6 inches (15 cm) of length.Logic gates can have propagation delays ranging from more than 10 ns down to the picosecond range, depending on the technology being  used. For delay calculation watch this video from UC-Burkeley

Setting time:  is the time elapsed from the application of an ideal instantaneous step input to the time at which the amplifier output has entered and remained within a specified error band, usually symmetrical about the final value[related to the output]


ADC: and make yourself familiar with difference of sampling (Nyquist rate),Quantization, and digitization DAC

IC gates  technology:

SSI: 1-11 gates

MSI: 12-100 gates

LSI: 100-10k gates

VLSI: above 10k gates

IC packing technology:

Dual side: DIP (Dual Inline Packaging)

  • First two letters are used to specify the manufacturers’ name e.g. ST is used for company named ST microelectronics.
  • Then we have 74/54 for TTL ICs. 74 is used for normal use ICs while 54 ICs are military-grade ICs and have higher operating temperature and are robust in voltage levels.
  • Next 2-letter tells us about the circuitry. E.g. LS is used for Low power Schottky i.e. schottky diodes and transistor are used in the circuitry to decrease the power supply.
  • And next letter tell us about the function of the IC e.g. 08 is for AND gate

Quad side: BCC: Bump Chip Carrier CLCC: Ceramic Leadless Chip Carrier Leadless chip carrier (LCC): Leadless Chip Carrier, contacts are recessed vertically. LCC: Leaded Chip Carrier LCCC: Leaded Ceramic Chip Carrier DLCC: Dual Lead-Less Chip Carrier (Ceramic) PLCC: Plastic Leaded Chip Carrier

IC transistor technology:

TTL: 5-volt power suppl;not sensitive to electrostatic discharge CMOS: 3-volt power supply-less power consumption

Digital measuring devices:

DMM: Digital Multi-meter Logic analyzer logic prob Pulser

Part 2) Number System, code:

Decimal, Binary, Binary number formats(Bit, Nibble, Byte, Word, Double word) Octal System,Hexadecimal System, and conversion between them (My C++ codes for these conversions )

Add, subtract (with/without compliment method),Multiplication, and division Compliments(r’s compliment, (r-1)’s compliment)-subtraction with these two

Rule of thumb (r-1’s compliment ): Start from LSD to the left, leave all the zeros, and first non-zero digit untouched, then invert all of higher significant digits

Rule of thumb (r’s compliment): Invert all digits one by one Codes: BCD-Excess code -Gray code (check out here to learn conversion).  (My C++ codes for these conversions),party bit Benefit of X-3: compliment 9 is obtained by compliment 1 in binary Benefit of Gray codes: In telecommunication and minimizing errors while transferring

Part 3) Binary logic

Logic gates (AND;represented by dot (.)- OR;epresented by plus (+), NOT;represented by bar or apostrophe (‘),XOR, NAND, NOR)

Truth table Boolean Algebra (Associative Law, Commutative Law, Identity element, Compliment, Boundedness Law, Distributive law, DeMorgan Law, Absorption law, Elimination law, Unique compliment theorem, Concensus theorem, Canonical forms:Min term, Max term)

Rule of thumb for min term: We put a 0 for the literal with compliment (‘) and a 1 for the literal without compliment and then take its binary equivalent

Rule of thumb for max term: We put a 1 for the literal with compliment (‘) and a 0 for the literal without compliment and then take its binary equivalent

Sum of products (SOP), Product of sums (POS)

Rule of thumb: The compliment of the function expressed in terms of sum of min terms can be obtained by taking sum of missing min terms in the original functions, and The compliment of the function expressed in terms of product of max terms can be obtained by taking product of max missing terms in the original functions

Rule of thumb for SOP, POS conversion: The function expressed in terms of product of max terms can be converted to sum of min terms or vice-versa can be done by interchanging π & ∑ and list the numbers which were missing from the original function.

Note: There is a limit on the extension of number of inputs which is known as fan-in Tri-state gates: High, Low, High Impedance(Z);Such gates have an extra input which is called enable input. Universal gates: NAND, NOR are called universal gates as any digital function can be implemented by using only NAND or NOR gate alone.

Combinational and sequential both type of circuits can be implemented using NAND or NOR gate

Special characteristics of ICs: Fan-out, Fan-in, Power dissipation (in mW),Propagation delay(nSec),Noise margin

Note: Some gates like XOR, BUFFER, INVERTER consume loading factor of 2 i.e. their load is equivalent to 2 usual gates.

Note: Noise margin should be as high as possible.

Note: By adjusting operating point of transistors, we can reduce the power dissipation of the gate but it increases delay in system .

Part 4) K-MAPS

Karnaugh map method (K-map), Don’t care, Redundant group,

Part 5) Combinational circuits

Adders (Half adder, Full adder);we can implement the Full Adder using 2 half adders and one OR gate.

Binary Adders : Serial adder, Parallel adder: Carry Ripple Adder or CRA(for n-bit adder we have the total time taken as (2n+1) Δ),Carry Look Ahead Adder CLA ()

Subtractors (Half Subtractor, Full Subtractor)

Binary Subtractor: Serial Subtractor, Parallel Subtractor,Subtraction using adder, Addition and subtraction using single circuit

Comparators: 1 Bit,2 Bit, Obtaining higher order comparator  from low order comparator

Encoder, Decoder: Implementing a full adder using 3-to-8 decoder, Obtaining higher decoder from lower decoders

Multiplexer, Demultiplexer: Boolean function implementation using MUX

Part 6) Sequential Circuits
The binary information stored in the memory element that is fed back into the circuit defines the state of the circuit
Synchronous circuits,Asynchronous circuits
Latches(LEVEL SENSITIVE): RS, D, JK, T ; There is a concern on timing of latches
Race around problem (PROBLEM IN JK & T LATCH):When we have J=1, K=1 or T=1 then output is complimented and if CLK (OR E) is still HIGH, then when the new output is fed back, output is complimented again and this way output is continuously complimented.
To Avoid, we can make sure that pulse width of the clock is less than the propagation delay of the Latch. Due to this restriction JK & T latches are generally not used in this form but as edge triggered flip-flops
Setup and Hold timeMETASTABLE STATE(METASTABILITY), propagation time (This is also called CLOCK TO Q delay)
Notes:  Hold time can be n negative which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time
To avoid setup time violations:

  • The combinational logic between the flip-flops should be optimized to get minimum delay.
  • Redesign the flip-flops to get lesser setup time.
  • Tweak launch flip-flop to have better slew at the clock pin, this will make launch flip-flop to be fast there by helping fixing setup violations.
  • Play with clock skew (useful skews).

To avoid hold time violations:

  • By adding delays (using buffers).
  • One can add lockup-latches (in cases where the hold time requirement is very huge, basically to avoid data slip).
Note: What is the difference between LATCH & FLIP-Flop?Ans:  We can easily find the answer after going through the theory given:

  1. Latches are level sensitive while flip-flops are edge sensitive devices
  2. Hence latches faces problems like glitches in the output while no such problem occurs in flip-flops.
  3. As we can see from different circuits given earlier, we need more gates to implement flip-flops than latches

Master slave flip-flop


Note: Maximum Frequency of the clock signal: check out these three nice questions

Tmin = CLK to Q delay + SETUP time+ c-delay

Fmax= 1/ Tmin = 1/( TCLK-to-Q + TSETUP+  c-delay)

Excitation table of FFs :  is actually exact opposite of what a truth table is. The truth table for the flip-flop gives us the output for the given combination of inputs and present output while an excitation table gives the input condition for the given output change.


1-RS flip-flop to D flip-flop

2-RS flip-flop to JK flip-flop

3-D Flip-flop to RS flip-flop:

4- D to T & T to D FF

Memory/ Registers

Counters: Ring/Johnson/ASYNCHRONOUS COUNTERS (Mod-2)/ Ripple counter (MOD-2n)/Counter other than MOD-2n

Down counter

Glitch:A glitch is an unwanted pulse which gets generated due to little difference in the delays of signals. Whenever signals with glitches are used as clock then glitches causes unwanted triggering of the flip-flop.

Clock Skew: It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times

Part 7) Specific Circuits

555 Timers: They are widely used and have two modes: Monostable, Astable

Schmitt Trigger: This is used to sharpen up falling and rising edges of DATA signal.

I just started gathering information. To review some interview questions on digital electronics check out here It will be completed shortly….


From → Cisco

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