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Testing of Digital Circuits

January 16, 2013


This topic is also known as timing analysis.

There three type of testing approaches in digital designs:

1-We design, without considering  a part for test inside the design, and after it we apply a test pattern to cover a large portion of the faults

2- Design for testablility. such as BIST (Built-In-Self-Test) normally come up with design i FPGA boards

3- Fault tolerant design: In this type of design, we consider a good margin to tolerate errors

Fault sources:

1- In design process: It can happen in two parts; specifications and implementation

2-Device defects

3-Manufacturing process: It happens in material

Fault types:

1- Dynamic: is more related to timing

2- Static: is more related to wiring faults, two wire close to each other and etc.

Test Models: (very simple fault model: Stuck-at faults)

1 – Stuck-at-0 (s-a-0)

2 – Stuck-at-1 (s-a-1)

Combinational Circuits- Test pattern generation

We have Fault vectors (F), and test vectors (T)

Fault Simulation: Given a test vector, by simulating the circuit with the fault, identify all the faults covered by the test vector, It the output is different this test vector can detect that fault

Test Generation:  Given a fault, identify all the test vectors which can cover that fault.

Limitations:  1-We expect one fault to occur[max] 2- Fault other than Stuck-at-fault are expected to show up as stuck-at-faults at some other location 3- these approaches are valid only for combinational circuits

Typical Circuit Enhancement:

1- Insertion of test points:  We increase  number of outputs

2-Pin amplification: We multiplex the function of the pin

3-Test modes:

4- Scan chains:  We can test all pins from a pin

Will be continued ….


From → Cisco

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