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Specific topics: [1] Metastabiliy or Quasistable

February 10, 2013


In metastable states, the circuit may be unable to settle into a stable ‘0’ or ‘1’ logic level within the time required for proper circuit operation. As a result, the circuit can act in unpredictable ways, and may lead to a system failure, sometimes referred to as a “glitch”

Metastable states are inherent features of asynchronous digital systems, and of systems with more than one independent clock domain. In self-timed asynchronous systems, arbiters are designed to allow the system to proceed only after the metastability has resolved, so the metastability is a normal condition, not an error condition. In synchronous systems with asynchronous inputs, synchronizes are designed to make the probability of a synchronization failure acceptably small. Metastable states are avoidable in fully synchronous systems when the input setup and hold time requirements on flip-flops are satisfied.synchronous systems with asynchronous inputs, synchronizers are designed to make the probability of a synchronization failure acceptably small. Metastable states are avoidable in fully synchronous systems when the input setup and hold time requirements on flip-flops are satisfied.

Metastabiliy happens under these situation:

  • When the input signal is an asynchronous signal.
  • When the clock skew/slew is too much (rise and fall time are more than the tolerable values).
  • When interfacing two domains operating at two different frequencies or at the same frequency but with different phase.
  • When the combinational delay is such that flip-flop data input changes in the critical window (setup+hold window)


An arbiter is a circuit designed to determine which of several signals arrive first. Arbiters are used in asynchronous circuits to order computational activities for shared resources to prevent concurrent incorrect operations. Arbiters are used on the inputs of fully synchronous systems, and also between clock domains, as synchronizers for input signals. Although they can minimize the occurrence of metastability to very low probabilities, all arbiters nevertheless have metastable states, which are unavoidable at the boundaries of regions of the input state space resulting in different outputs

For more information check out this paper

Synthesizer or a synchronization register chain and working in different clock domains:


Synchronous circuit design techniques make digital circuits that are resistant to the failure modes that can be caused by metastability. A clock domain is defined as a group of flip-flops with a common clock. Such architectures can form a circuit guaranteed free of metastability (below a certain maximum clock frequency, above which first metastability, then outright failure occur), assuming a low-skew common clock. However, even then, if the system has a dependence on any continuous inputs then these are likely to be vulnerable to metastable states.

When synchronous design techniques are used, protection against metastable events causing systems failures need only be provided when transferring data between different clock domains or from an unclocked region into the synchronous system. This protection can often take the form of a series of delay flip-flops which delay the data stream long enough for the metastability to have statistically been removed.

One remedy in this case is the use of a two-stage synchronization circuit.The second flip-flop receives the output signal of the first stage one clock period later and can go into a metastable state only if its input conditions are also violated. That is, the output of the first flip-flop is still metastable during its setup and hold time


For more details, study this Texas Instrument document, Altera document


From → Cisco

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