Cisco is **NETWORKING** based company. You **MUST** have at least the minimum knowledge, and taste of network with you. You can also get CCNA,and CCNP degrees from Cisco..

In the following post. I do my best to transfer to main important concepts

Part 1: Introduction to networking:

**Modems** : This is the very first device between your equipment that connect your computers to** the internet cloud.**[DSL or Digital Subscriber Line(12Mbps is the Maximum of this technology, Asynchronous and download is faster than upload, and speed is always fix), T1, T2,T3, cable, fiber optic,comcast modems]

**Routers**: behind the modem, there is device called router, and it responsible for routing data in the network

**Firewalls**: underneath the router, firewall exists to protect your device from hackers

**Switches: **is located under firewall as the spliter of internet signal : HUBs was old concept of Switches. JUST trow them in garbage. Hub has no intelligent and basically split internet between users and it causes problem, but Switches knows how to transfer data. Switches may have different ports from 4 to hundred, thousands. We have managed and un-managed switch. Manage version allows you to go into the switch and program to do certain things like quality of the service.. 10Mbps[old days]/100Mbps[nowadays]/ 1000Mbps [latest technology]

**Wireless Access Points: **will allow wireless devices, and computers to connect to your network. standards are 802.11 family [a[old and nobody use them nowadays, and is not compatible with other standard], b[11Mbps],g,n[allows much larger area to cover, faster, suitable for VOIP],ac]

**Defines Logical and Physical: **[Not necessary the same concepts]. For example physically you may have one device including modem+ router + firewall + Switch but logically they for devices. Even you may connect your computer to a switch share with other computer but you not logically connected to the same network

**Speed** :first of all b=bit and B=Byte and the you should know that speed is measured in bps means bit per second

**VPN**: Virtual Private Network.: Somebody out of physical network becomes a member of your internal network

**Cabling : **jack-patch panel

** Clients, Devices and Servers: **Everything on the network is called network device, Server:is a network device that provide something for the rest of the network, Clients: is a network device that receives ar service from service

Part 2: Understanding broadband technologies

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I learnt Python from Google Developer Python class, and I recommend you to start learning it as a fast scripting language.

]]>In metastable states, the circuit may be unable to settle into a stable ‘0’ or ‘1’ logic level within the time required for proper circuit operation. As a result, the circuit can act in unpredictable ways, and may lead to a system failure, sometimes referred to as a “glitch”

Metastable states are inherent features of **asynchronous digital systems**, and of **systems with more than one independent clock domain**. In self-timed asynchronous systems, arbiters are designed to allow the system to proceed only after the metastability has resolved, so the metastability is a normal condition, not an error condition. In synchronous systems with asynchronous inputs, synchronizes are designed to make the probability of a synchronization failure acceptably small. Metastable states are avoidable in fully synchronous systems when the input setup and hold time requirements on flip-flops are satisfied.synchronous systems with asynchronous inputs, synchronizers are designed to make the probability of a synchronization failure acceptably small. Metastable states are avoidable in fully synchronous systems when the input setup and hold time requirements on flip-flops are satisfied.

Metastabiliy happens under these situation:

- When the input signal is an asynchronous signal.
- When the clock skew/slew is too much (rise and fall time are more than the tolerable values).
- When interfacing two domains operating at two different frequencies or at the same frequency but with different phase.
- When the combinational delay is such that flip-flop data input changes in the critical window (setup+hold window)

**Arbiter**:

An *arbiter* is a circuit designed to determine which of several signals arrive first. Arbiters are used in asynchronous circuits to order computational activities for shared resources to prevent concurrent incorrect operations. Arbiters are used on the inputs of fully synchronous systems, and also between clock domains, as synchronizers for input signals. Although they can minimize the occurrence of metastability to very low probabilities, all arbiters nevertheless have metastable states, which are unavoidable at the boundaries of regions of the input state space resulting in different outputs

For more information check out this paper

**Synthesizer or a synchronization register chain and working in different clock domains:**

Synchronous circuit design techniques make digital circuits that are resistant to the failure modes that can be caused by metastability. A *clock domain* is defined as a group of flip-flops with a common clock. Such architectures can form a circuit guaranteed free of metastability (below a certain maximum clock frequency, above which first metastability, then outright failure occur), assuming a low-skew common clock. However, even then, if the system has a dependence on any continuous inputs then these are likely to be vulnerable to metastable states.^{
}

When synchronous design techniques are used, protection against metastable events causing systems failures need only be provided when transferring data between different clock domains or from an unclocked region into the synchronous system. This protection can often take the form of a series of delay flip-flops which delay the data stream long enough for the metastability to have statistically been removed.

One remedy in this case is the use of a two-stage synchronization circuit.The second flip-flop receives the output signal of the first stage one clock period later and can go into a metastable state only *if its input conditions are also violated. That is, the output of the first flip-flop is still metastable during its setup and hold time*

For more details, study this Texas Instrument document, Altera document

]]>**This topic is also known as timing analysis.**

There three type of testing approaches in digital designs:

1-We design, without considering a part for test inside the design, and after it we apply a test pattern to cover a large portion of the faults

2- Design for testablility. such as BIST (Built-In-Self-Test) normally come up with design i FPGA boards

3- Fault tolerant design: In this type of design, we consider a good margin to tolerate errors

Fault sources:

1- In design process: It can happen in two parts; specifications and implementation

2-Device defects

3-Manufacturing process: It happens in material

Fault types:

1- Dynamic: is more related to timing

2- Static: is more related to wiring faults, two wire close to each other and etc.

Test Models: (very simple fault model: Stuck-at faults)

1 – Stuck-at-0 (s-a-0)

2 – Stuck-at-1 (s-a-1)

Combinational Circuits- Test pattern generation

We have Fault vectors (F), and test vectors (T)

Fault Simulation: Given a test vector, by simulating the circuit with the fault, identify all the faults covered by the test vector, It the output is different this test vector can detect that fault

Test Generation: Given a fault, identify all the test vectors which can cover that fault.

Limitations: 1-We expect one fault to occur[max] 2- Fault other than Stuck-at-fault are expected to show up as stuck-at-faults at some other location 3- these approaches are valid only for combinational circuits

Typical Circuit Enhancement:

1- Insertion of test points: We increase number of outputs

2-Pin amplification: We multiplex the function of the pin

3-Test modes:

4- Scan chains: We can test all pins from a pin

Will be continued ….

]]>Note: What in many other programming languages can only be done with loops, Matlab can often do with vectors

Desktop calculations:1-At the end of each command line putting

;will not echo the input2- Arithmetic:

+ – * / \(left and right divisions, note that MATLAB has two operation for division)^: Then 6/3 is 2 and 3\6 is 2, too.3- Last line editing: by pressing

Up/Down buttons; you can recall the last line4- A few built-in functions:

sin(x), cos(x), tan(x), sqrt(x), exp(x), log(x), log10(x), acos(x), asin(x), atan(x), atan2(x,y)5- Naming constants and variables

: MATLAB is Case-sensitive. Therefore, Pi, Pi, PI; pi are different 7- Format: 5 digits display is default, but 15 digits display can be achieved by command:format long, for scientific nation command isformat short e.6- Cleaning the screen:

clc7- NaN : Not a Number : I got reject from a company by not knowing it. These values result from operations which have undefined numerical results

One-dimensional arrays

1-Define a row and column matrix: space and comma are equal [1 2 3] = [1,2,3]

2-Indexing for a

matrix(x,y)3- Size of a matrix:

size(Matrix),Length of vector:length(Matrix)4- Clearing variables:

clear5- Add/subtract to matrix

A+B.A-B, array multiplicationA.*B, array divisionA./B. Array powerA.^n6- Defining equally distance elements,

A=[1:1:10];7-Simple plots:

plot(x,y,’color’), grid on/off, xlabel(‘’), ylabel(‘’), figure, hold on/off, hist(Y,X)Matrices

1- Defining a matrix:

A=[1 2 3;4 5 6]2- Juxtaposition and sub matrix C

= [A B], C=[A;B], C=A(:,1), A(:,1), A(1:2,1:2’]3- Elementary operations with matrices

A+B, A-B, A.*B and A*B, A./B4-

ones(m,n), zeros(m,n)Complex numbers

1-imaginary unit is i or j but j is preferred professionally, since, ‘i’ is as current unit in electrical engineering , note that there is no need to write * before i,j

2- real part:

real(Z),imaginary part: imag(Z),magnitudeabs(Z), angle byangle(Z)3- Arrays of complex numbers

System of linear equations:

AX=B1- Determinant:

det(A)2- Crammer’s rule:

X=[det(D1);det(D2);det(D3)]/det(A), D1=A, D1(:,1)=B, D2=A, D2(:,2)=B, …..3- Matrix inversion

inv(A)4-Solving systems of linear equations in MATLAB

Polynomials

1-Polynomial representation: by its coefficients

2- Getting roots:

roots(coeff)3- Multiplication is achieved by convolving

conv(c1,c2)4-Division is achieved by deconvolving

deconv(c1,c2)Programming in MATLAB

1- Programming a function:

function y=Alan(x1, x2)2- Repetitive control structure- FOR LOOPS: e.g.

for K=1:1:10P(1,k) =sqrt(k);End3- Conditional control structure:

If condition

Expression

Elseif condition>>>>>> look at the here elseif are one work but in C++ it was else if

Expression

Expression

Else

Expression

end4- Repetitive control structure-

WHILE LOOPExternal files and programs:

1-Saving data:

save filename.mat variable / save(filename, variables)2- Loading data

X=load(filename.)Differential and integral

1- Calculating differential:

diff(x)/interval: consider that length of diff(x) is less that length of x2- Calculating Integral

: sum(x)*intervalWorking with stringsString in MATLAB are string of characters

- Alway use single quote to define a string
- Adding two strings of x,y back to back is possible by
strcat() , using + sign is a mistake- Several ways to print a string out to workspace: Formatting strings in MATLAB:
Type the name of the variablew/o a trailing semicolon

disp()is almost the same as above, except it does not print out the variable namefprintf()is for formatting text and printing out to a file or other device, such as the workspace. It is a very powerful command for formatting strings, combining them, and printing them outsprintf()is for formatting text in order to create new string variable- Note that : using cell array for many elements are better that making matrix of the names = [‘Jonas’,’Fred’,’John’] meansnames = JonasFredJohn butnames = {‘Jonas’,’Fred’,’John’} means names = ‘Jonas’ ‘Fred’ ‘John’

Cells and structures;

- Cell arrays can mix and match data types
- Structures can be used to organize and group information

Working with files

fopen()-> fid = fopen(filename, permission) ; fid: number returned by fopen which you will use to refer to this file, permission: ‘r’,’w’, ‘a’fclose()- Other ways to write to files:
ìcsvwrite(), ìdlmwrite()>> myFileID = fopen(‘testfile.txt’,’w’)

myFileID = 3

>> x = 100;

>> fprintf(myFileID,’X isequal to %d\n’,x);

>> fclose(myFileID);

ps: I found this video channel for you. unfortunately, it has no voice. pps: More tutorials: **Introduction to MATLAB** by D.F. Griffiths

]]>Embedded system is a computer system designed for specific control functions, normally for real-time purposes and it’s part of a complete system with a hardware and mechanical parts. Physically, embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure, Prices vary from under dollar to hundred dollars.

The core of an embedded system can be a microcontroller,DSP, CPLD or FPGA . The difference between these cores and CPU is lack of having MMU(memory management unit) and their application in real-time functions.

The best tutorial that, I found on the web on embedded system programming so far is in the following link by Arvind Singh from Bangalore

The following chapters are covered:

- Chapter-1: Introduction to Embedded Systems
- Chapter-2: Instruction Sets
- Chapter-3: Keil C Programming Tutorial (Part-1)
- Chapter-4: Keil C Programming Tutorial: Pointers
- Chapter-5: Keil C Programming Tutorial: Functions
- Chapter-6: Keil C Programming Tutorial: Writing simple C program in Keil
- Chapter-7: Keil C Programming Tutorial: C and Assembly together
- Chapter-8: Keili C Programming Tutorial: Interfacing C programs to assembeler
- Chapter-9: How to use Keil Microvision IDE
- Chapter-10: Interrupts Programming 8051
- Chapter-11: Timers in 8051 &Timer Programming
- Chapter-12: USART Programming
- Chapter-13: I2C or TWI(Two Wire Interface)

You can download Keil C from from this site and instantly start programming!

Check out these videos by Dr. Santanu Chaudhury, Department of Electrical Engineering, if you need to learn more.

What is next? Making yourself familiar with Raspberry Pi and Arduino

Raspberry Pi Website and this YouTube channel are the best places to learn Raspberry Pi

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I am uploading a series of videos on my YouTube channel , but it’s matter of time. Please subscribe. and get the latest updates

Meanwhile, I introduce the following:

- Testbench.in : System Verilog and VMM tutorial with a lots of example
- Asicguru.com : Another nice SV tutorial site
- Doulos SV Tutorial : Not that much extensive, but still good
- Another decent tutorial from Project-Veripage
- SV Tutorial from ASIC-World. It is not yet complete, but once it is complete, then it will be another great site to learn SV.

You can easily learn VHDL from my YouTube videos very fast

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Duty cycle: Pulse width/Period

Rise time: time from %10 of pulse amplitude to %90 of pulse amplitude [For the step function]

Fall time: time from %90 of pulse amplitude to %10 of pulse amplitude [For the step function]

Transition time: Switching time between two valid states: can be Rise time or Fall time [For the step function]

Propagation delay/gate delay: Time that response changes from initial value to %50 of final value. Propagation delay increases with operating temperature.The term low,high speed comes from propagation delay. Wires have an approximate propagation delay of 1 ns for every 6 inches (15 cm) of length.Logic gates can have propagation delays ranging from more than 10 ns down to the picosecond range, depending on the technology being used. For delay calculation watch this video from UC-Burkeley

Setting time:is the time elapsed from the application of an ideal instantaneous step input to the time at which the amplifier output has entered and remained within a specified error band, usually symmetrical about the final value[related to the output]

Converters:

ADC: and make yourself familiar with difference of sampling (Nyquist rate),Quantization, and digitization DAC

IC gates technology:

SSI: 1-11 gates

MSI: 12-100 gates

LSI: 100-10k gates

VLSI: above 10k gates

IC packing technology:

Dual side:DIP (Dual Inline Packaging)

- First two letters are used to specify the manufacturers’ name e.g. ST is used for company named ST microelectronics.
- Then we have 74/54 for TTL ICs. 74 is used for normal use ICs while 54 ICs are military-grade ICs and have higher operating temperature and are robust in voltage levels.
- Next 2-letter tells us about the circuitry. E.g. LS is used for Low power Schottky i.e. schottky diodes and transistor are used in the circuitry to decrease the power supply.
- And next letter tell us about the function of the IC e.g. 08 is for AND gate

Quad side:BCC: Bump Chip CarrierCLCC: Ceramic Leadless Chip Carrier Leadless chip carrier (LCC): Leadless Chip Carrier, contacts are recessed vertically.LCC: Leaded Chip CarrierLCCC:Leaded Ceramic Chip CarrierDLCC:Dual Lead-Less Chip Carrier (Ceramic)PLCC: Plastic Leaded Chip Carrier

IC transistor technology:

TTL: 5-volt power suppl;not sensitive to electrostatic dischargeCMOS: 3-volt power supply-less power consumption

Digital measuring devices:

DMM: Digital Multi-meter Logic analyzer logic prob Pulser

Part 2) Number System, code:

Decimal, Binary, Binary number formats(Bit, Nibble, Byte, Word, Double word) Octal System,Hexadecimal System, and conversion between them (My C++ codes for these conversions )

Add, subtract (with/without compliment method),Multiplication, and division Compliments(r’s compliment, (r-1)’s compliment)-subtraction with these two

Rule of thumb (r-1’s compliment ): Start from LSD to the left, leave all the zeros, and first non-zero digit untouched, then invert all of higher significant digits

Rule of thumb (r’s compliment): Invert all digits one by one Codes: BCD-Excess code -Gray code (check out here to learn conversion). (My C++ codes for these conversions),party bit Benefit of X-3: compliment 9 is obtained by compliment 1 in binary Benefit of Gray codes: In telecommunication and minimizing errors while transferring

Part 3) Binary logic

Logic gates (AND;represented by dot (.)- OR;epresented by plus (+), NOT;represented by bar or apostrophe (‘),XOR, NAND, NOR)

Truth table Boolean Algebra (

Associative Law,)Commutative Law,Identity element,Compliment,Boundedness Law,Distributive law,DeMorgan Law,Absorption law,Elimination law,Unique compliment theorem, Concensus theorem, Canonical forms:Min term,Max termRule of thumb for min term: We put a 0 for the literal with compliment (‘) and a 1 for the literal without compliment and then take its binary equivalent

Rule of thumb for max term: We put a 1 for the literal with compliment (‘) and a 0 for the literal without compliment and then take its binary equivalent

Sum of products (SOP),Product of sums (POS)Rule of thumb: The compliment of the function expressed in terms of sum of min terms can be obtained by taking sum of missing min terms in the original functions, and The compliment of the function expressed in terms of product of max terms can be obtained by taking product of max missing terms in the original functions

Rule of thumb for SOP, POS conversion: The function expressed in terms of product of max terms can be converted to sum of min terms or vice-versa can be done by interchanging π & ∑ and list the numbers which were missing from the original function.

Note: There is a limit on the extension of number of inputs which is known asfan-inTri-state gates: High, Low, High Impedance(Z);Such gates have an extra input which is called enable input. Universal gates: NAND, NOR are called universal gates as any digital function can be implemented by using only NAND or NOR gate alone.Combinational and sequential both type of circuits can be implemented using NAND or NOR gate

Special characteristics of ICs:

Fan-out,Fan-in,Power dissipation (in mW),Propagation delay(nSec),Noise marginNote: Some gates like

XOR,BUFFER,INVERTERconsume loading factor of 2 i.e. their load is equivalent to 2 usual gates.Note: Noise margin should be as high as possible.

Note: By adjusting operating point of transistors, we can reduce the power dissipation of the gate but it increases delay in system .

Part 4) K-MAPS

Karnaugh map method (K-map), Don’t care, Redundant group,

Part 5) Combinational circuits

Adders(Half adder, Full adder);we can implement the Full Adder using 2 half adders and oneOR gate.

Binary Adders: Serial adder, Parallel adder: Carry Ripple Adder or CRA(for n-bit adder we have the total time taken as (2n+1) Δ),Carry Look Ahead Adder CLA ()

Subtractors(Half Subtractor, Full Subtractor)

Binary Subtractor: Serial Subtractor, Parallel Subtractor,Subtraction using adder, Addition and subtraction using single circuit

Comparators: 1 Bit,2 Bit, Obtaining higher order comparator from low order comparator

Encoder, Decoder: Implementing a full adder using 3-to-8 decoder, Obtaining higher decoder from lower decoders

Multiplexer, Demultiplexer: Boolean function implementation using MUX

Part 6) Sequential Circuits

The binary information stored in the memory element that is fed back into the circuit defines the state of the circuitSynchronous circuits,Asynchronous circuitsFALLING (TRAILING) EDGE, RISING EDGEFLIP-FLOP (FF) orBISTABLE MULTIVIBRATORLatches(: RS, D, JK, T ; There is a concern on timing of latchesLEVEL SENSITIVE)Race around problem (When we have J=1, K=1 or T=1 then output is complimented and if CLK (OR E) is still HIGH, then when the new output is fed back, output is complimented again and this way output is continuously complimented.PROBLEM IN JK & T LATCH):To Avoid, we can make sure that pulse width of the clock is less than the propagation delay of the Latch. Due to this restriction JK & T latches are generally not used in this form but as edge triggered flip-flopsSetup and Hold time,propagation time (This is also called CLOCK TO Q delay)METASTABLE STATE(METASTABILITY),Notes:Hold time can be n negative which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold timeTo avoid setup time violations:

- The combinational logic between the flip-flops should be optimized to get minimum delay.
- Redesign the flip-flops to get lesser setup time.
- Tweak launch flip-flop to have better slew at the clock pin, this will make launch flip-flop to be fast there by helping fixing setup violations.
- Play with clock skew (useful skews).
To avoid hold time violations:

- By adding delays (using buffers).
- One can add lockup-latches (in cases where the hold time requirement is very huge, basically to avoid data slip).
Note:What is the difference between LATCH & FLIP-Flop?Ans: We can easily find the answer after going through the theory given:

- Latches are level sensitive while flip-flops are edge sensitive devices
- Hence latches faces problems like glitches in the output while no such problem occurs in flip-flops.
- As we can see from different circuits given earlier, we need more gates to implement flip-flops than latches

Master slave flip-flop

PROBLEM IN MASTER SLAVE:Note: Maximum Frequency of the clock signal: check out these three nice questions

T_{min}= CLK to Q delay + SETUP time+ c-delay

F_{max}= 1/ T_{min}= 1/( T_{CLK-to-Q}+ T_{SETUP+ c-delay})Excitation table of FFs : is actually exact opposite of what a truth table is. The truth table for the flip-flop gives us the output for the given combination of inputs and present output while an excitation table gives the input condition for the given output change.

CONVERSION OF ONE FLIP-FLOP TO OTHER1-RS flip-flop to D flip-flop

2-RS flip-flop to JK flip-flop

3-D Flip-flop to RS flip-flop:

4- D to T & T to D FF

Memory/ Registers

Counters: Ring/Johnson/ASYNCHRONOUS COUNTERS (Mod-2)/ Ripple counter (MOD-2

^{n})/Counter other than MOD-2^{n}Down counter

Glitch:Aglitch is an unwanted pulse which gets generated due to little difference in the delays of signals. Whenever signals with glitches are used as clock then glitches causes unwanted triggering of the flip-flop.

Clock Skew:It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times

Part 7) Specific Circuits

555 Timers:They are widely used and have two modes: Monostable, Astable

Schmitt Trigger:This is used to sharpen up falling and rising edges of DATA signal.

I just started gathering information. To review some interview questions on digital electronics check out here It will be completed shortly….

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